At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Prior 7-12 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)Should possess intimate knowledge of DFT insertion flowsBasic scan chain insertion using synthesis or other software toolsExperience in compression scan insertion, LBIST and other scan technologiesIntimate knowledge of memory build-in self-test (MBIST)Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goalsDebug and Analysis of failures to improve fault coverageVerification of ATPG testbenches and debugging root cause of simulation mis-comparesWorking knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687Knowledge of timing analysis and equivalency checks would be added bonusAbility to work in collaborative team environment