Senior ASIC Physical Design Engineer
Google • Sunnyvale, CA • Posted July 15, 2026
Position Overview
Senior ASIC Physical Design Engineer
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure).
+ Experience in Python, Tcl, or Perl scripting.
**Preferred qualifications:**
+ Experience working with external partners on Physical Design (PD) closure.
+ Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates.
+ Experience with Synopsys/Cadence PnR tools.
+ Experience with backend flows (e....
_corporate_fare_ Google _place_ Sunnyvale, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure).
+ Experience in Python, Tcl, or Perl scripting.
**Preferred qualifications:**
+ Experience working with external partners on Physical Design (PD) closure.
+ Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates.
+ Experience with Synopsys/Cadence PnR tools.
+ Experience with backend flows (e....